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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13714-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90460 Series
MB90462/467/F462/V460
s DESCRIPTION
The MB90460 series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. While inheriting the AT architecture of the F2MC* family, the instruction set for the F2MC-16LX CPU core of the MB90460 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90460 has an on-chip 32-bit accumulator which enables processing of long-word data. The peripheral resources integrated in the MB90460 series include : an 8/10-bit A/D converter, UARTs (SCI) 0 to 1, 16-bit PPG timer, a multi-functional timer (16-bit free-run timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 and 5, 16-bit PPG timer, a waveform generator) , a multi-pulse generator (16-bit PPG timer, 16-bit reload timer, waveform sequencer) , PWC 0 to 1, 16-bit reload timer and DTP/external interrupt. * : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
s FEATURES
* Minimum execution time : 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4 * Maximum memory space 16 Mbyte Linear/bank access (Continued) 64-pin plastic QFP 64-pin plastic LQFP 64-pin plastic SH-DIP
s PACKAGES
(FPT-64P-M06)
(FPT-64P-M09)
(DIP-64P-M01)
MB90460 Series
(Continued) * Instruction set optimized for controller applications Supported data types : bit, byte, word, and long-word types Standard addressing modes : 23 types 32-bit accumulator enhancing high-precision operations Signed multiplication/division and extended RETI instructions * Enhanced high level language (C) and multi-tasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed : 4 byte instruction queue * Enhanced interrupt function Up to eight programmable priority levels External interrupt inputs : 8 lines * Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs : 8 lines * Internal ROM FLASH : 64 Kbyte (with flash security) MASKROM : 64 Kbyte * Internal RAM EVA : 8 Kbyte FLASH : 2 Kbyte MASKROM : 2 Kbyte * General-purpose ports Up to 51 channels (Input pull-up resistor settable for : 16 channels) * A/D Converter (RC) : 8 ch 8/10-bit resolution selectable Conversion time : 6.13 s (Min) , 16 MHz operation * UART : 2 channels * 16 bit PPG : 3 channels Mode switching function provided (PWM mode or one-shot mode) Can be worked with a multi-functional timer, a multi-pulse generator or individually * 16 bit reload timer : 2 channels Can be worked with multi-pulse generator or individually * 16-bit PWC timer : 2 channels * A multi-functional timer Input capture : 4 channels Output compare with selectable buffer : 6 channels Free-run timer with up or up/down mode selection and selectable buffer : 1 channel 16-bit PPG : 1 channel A waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time) * A multi-pulse generator 16-bit PPG : 1 channel 16-bit reload timer : 1 channel Waveform sequencer : (16-bit timer with buffer and compare clear function) * Time-base counter/watchdog timer : 18-bit
2
MB90460 Series
* Low-power consumption mode : Sleep mode Stop mode CPU intermittent operation mode * Package : QFP-64 (FPT-64P-M09 : 0.65 mm pitch) QFP-64 (FPT-64P-M06 : 1.00 mm pitch) SDIP-64 (DIP-64P-M01 : 1.78 mm pitch) * CMOS technology
3
MB90460 Series
s PRODUCT LINEUP
Part number Item Classification ROM size RAM size MB90V460 Development/evaluation product MB90F462 Mass-produced products (Flash ROM) MB90462 MB90467
Mass-produced products (Mask ROM)
CPU function
I/O port
64 KBytes 8 KBytes 2 KBytes Number of Instruction : 351 Minimum execution time : 62.5 ns / 4 MHz (PLL x 4) Addressing mode : 23 Data bit length : 1, 8, 16 bits Maximum memory space : 16 MBytes I/O port (CMOS) : 51 Pulse width counter timer : 2 channels
Pulse width counter timer : 1ch
PWC
UART
16-bit reload timer
16-bit PPG timer Multi-functional timer (for AC/DC motor control)
Multi-pulse generator (for DC motor control) 8/10-bit A/D converter DTP/External interrupt Lower power consumption
Timer function (select the counter timer from three internal clocks) Various Pulse width measuring function (H pulse width, L pulse width, rising edge to falling edge period, falling edge to rising edge period, rising edge to rising edge period and falling edge to falling edge period) UART : 2 channels With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used Transmission can be one-to-one (bi-directional commuication) or one-to-n (MasterSlave communication) Reload timer : 2 channels Reload mode, single-shot mode or event count mode selectable Can be worked with a multi-pulse generator or individually PPG timer : 3 channels PPG timer : 2ch PWM mode or single-shot mode selectable Can be worked with multi-functional timer / multi-pulse generator or individually 16-bit free-running timer with up or up/down mode selection and buffer : 1 channel 16-bit output compare : 6 channels 16-bit input capture : 4 channels 16-bit PPG timer : 1 channel Waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time) 16-bit PPG timer : 1 channel 16-bit reload timer operation (toggle output, one shot output selectable) Event counter function : 1 channel built-in A waveform sequencer (includes 16-bit timer with buffer and compare clear function) 8/10-bit resolution (8 channels) Conversion time : Less than 6.13 S (16 MHz internal clock) 8 independent channels Selectable causes : Rising edge, falling edge, "L" level or "H" level Stop mode / Sleep mode / CPU intermittent operation mode
(Continued)
4
MB90460 Series
(Continued) Part number Item
Package Power supply voltage for operation* Process
MB90V460
MB90F462
MB90462
MB90467
PGA256
LQFP-64 (FPT-64P-M09 : 0.65 mm pitch) QFP-64 (FPT-64P-M06 : 1.00 mm pitch) SDIP-64 (DIP-64P-M01 : 1.78 mm pitch) 4.5 V to 5.5 V * CMOS
* : Varies with conditions such as the operating frequency (See section "s ELECTRICAL CHARACTERISTICS") . Assurance for the MB90V460 is given only for operation with a tool at a power supply voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25 C, and an operating frequency of 1 MHz to 16 MHz.
s PACKAGE AND CORRESPONDING PRODUCTS
Package PGA256 FPT-64P-M09 FTP-64P-M06 DIP-64P-M01 : Available, x : Not available Note : For more information about each package, see section "s PACKAGE DIMENSIONS". x x x MB90V460 MB90F462 x MB90462 x MB90467 x
s DIFFERENCES AMONG PRODUCTS
Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. * The MB90V460 does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V460, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are mapped to bank FF only. (This setting can be changed by configuring the development tool.) * In the MB90462/F462/467, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are mapped to bank FF only.
5
MB90460 Series
s PIN ASSIGNMENT
(TOP VIEW)
P43/SNI0*2 P42/SCK0 P41/SOT0 P40/SIN0 P37/PPG0 P36/PPG1*2 C VCC P35*1/RTO5 (Z) P34*1/RTO4 (W) P33*1/RTO3 (Y) P32*1/RTO2 (V) P31*1/RTO1 (X) P44/SNI1*2 P45/SNI2*2 P46/PPG2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7 MD0 64 63 62 61 60 59 58 57 56 55 54 53 52
*1 : Heavy current pins *2 : MB90V460, MB90F462, MB90462 only. They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and waveform sequencer.
RST MD1 MD2 X0 X1 VSS P00*1/OPT0*2 P01*1/OPT1*2 P02*1/OPT2*2 P03*1/OPT3*2 P04*1/OPT4*2 P05*1/OPT5*2 P06/PWI0*2
20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P30*1/RTO0 (U) VSS P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1*2 P11/INT1 P10/INT0/DTTI0 P07/PWO0*2
(FPT-64P-M06)
(Continued)
6
MB90460 Series
(TOP VIEW)
P44/SNI1*2 P43/SNI0*2 P42/SCK0 P41/SOT0 P40/SIN0 P37/PPG0 P36/PPG1*2 C VCC P35*1/RTO5 (Z) P34*1/RTO4 (W) P33*1/RTO3 (Y) P32*1/RTO2 (V) P31*1/RTO1 (X) P30*1/RTO0 (U) VSS P45/SNI2*2 P46/PPG2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
*1 : Heavy current pins *2 : MB90V460, MB90F462, MB90462 only. They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and waveform sequencer.
P63/INT7 MD0 RST MD1 MD2 X0 X1 VSS P00*1/OPT0*2 P01*1/OPT1*2 P02*1/OPT2*2 P03*1/OPT3*2 P04*1/OPT4*2 P05*1/OPT5*2 P06/PWI0 P07/PWO0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1*2 P11/INT1 P10/INT0/DTTI0
(FPT-64P-M09)
(Continued)
7
MB90460 Series
(Continued)
(TOP VIEW)
C P36/PPG1*2 P37/PPG0 P40/SIN0 P41/SOT0 P42/SCK0 P43/SNI0*2 P44/SNI1*2 P45/SNI2*2 P46/PPG2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7 MD0 RST MD1 MD2 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC P35*1/RTO5 (Z) P34*1/RTO4 (W) P33*1/RTO3 (Y) P32*1/RTO2 (V) P31*1/RTO1 (X) P30*1/RTO0 (U) VSS P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1*2 P11/INT1 P10/INT0/DTTI0 P07/PWO0*2 P06/PWI0*2 P05*1/OPT5*2 P04*1/OPT4*2 P03*1/OPT3*2 P02*1/OPT2*2 P01*1/OPT1*2 P00*1/OPT0*2
(DIP-64P-M01) *1 : Heavy current pins *2 : MB90V460, MB90F462, MB90462 only. They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and waveform sequencer.
8
MB90460 Series
s PIN DESCRIPTION
Pin No. QFPM06*2 23, 24 20 LQFPSDIP*3 M09*1 22, 23 19 30, 31 27 Pin name X0, X1 RST P00 to P05 26 to 31 25 to 30 33 to 38 OPT0 to OPT5*4 P06 PWI0*4 P07 PWO0* P10 34 33 41 INT0 DTTI0 P11 35 34 42 INT1 P12 36 35 43 INT2 DTTI1*4 P13 to P14 INT3 to INT4 P15 39 38 46 INT5 TIN0 C C C C
4
I/O circuit A B Oscillation input pins. External reset input pin. General-purpose I/O ports. D
Function
Output terminals OPT0 to 5 of the waveform sequencer. These pins output the waveforms specified at the output data registers of the waveform sequencer circuit. Output is generated when OPE0 to 5 of OPCR is enabled.*4 General-purpose I/O ports. PWC 0 signal input pin.*4 General-purpose I/O ports. PWC 0 signal output pin.*4 General-purpose I/O ports. Can be used as interrupt request input channels 0. Input is enabled when 1 is set in EN0 in standby mode. RTO0 to 5 pins for fixed-level input. This function is enabled when the waveform generator enables its input bits. General-purpose I/O ports. Can be used as interrupt request input channels 1. Input is enabled when 1 is set in EN1 in standby mode. General-purpose I/O ports. Can be used as interrupt request input channels 2. Input is enabled when 1 is set in EN2 in standby mode. OPT0 to 5 pins for fixed-level input. This function is enabled when the waveform sequencer enables its input bit.*4 General-purpose I/O ports.
32 33
31 32
39 40
E E
37 to 38
36 to 37
44 to 45
C
Can be used as interrupt request input channels 3 to 4. Input is enabled when 1 is set in EN3 to EN4 in standby mode. General-purpose I/O ports. Can be used as interrupt request input channel 5. Input is enabled when 1 is set in EN5 in standby mode. External clock input pin for reload timer 0.
(Continued)
9
MB90460 Series
Pin No. QFPM06*2 LQFPSDIP*3 M09*1
Pin name P16
I/O circuit General-purpose I/O ports. C
Function
40
39
47
INT6 TO0
Can be used as interrupt request input channels 6. Input is enabled when 1 is set in EN6 in standby mode. Event output pin for reload timer 0. General-purpose I/O ports. External clock input pin for free-running timer. General-purpose I/O ports. External clock input pin for reload timer 1. General-purpose I/O ports. Event output pin for reload timer 1. General-purpose I/O ports. PWC 1 signal input pin. General-purpose I/O ports. PWC 1 signal output pin. General-purpose I/O ports.
41 42 43 44 45
40 41 42 43 44
48 49 50 51 52
P17 FRCK P20 TIN1 P21 TO1 P22 PWI1 P23 PWO1 P24 to P27
C F F F F
46 to 49
45 to 48
53 to 56
IN0 to IN3 P30 to P35
F
Trigger input pins for input capture channels 0 to 3. When input capture channels 0 to 3 are used for input operation, these pins are enabled as required and must not be used for any other I/P. General-purpose I/O ports.
51 to 56
50 to 55
58 to 63
RTO0 (U) to RTO5 (Z) P36
G
Waveform generator output pins. These pins output the waveforms specified at the waveform generator. Output is generated when waveform generator output is enabled. (U) to (Z) show the coils that control 3-phase motor. General-purpose I/O ports. Output pins for PPG channels 1. This function is enabled when PPG channels 1 enable output.*4 General-purpose I/O ports. Output pins for PPG channels 0. This function is enabled when PPG channels 0 enable output. General-purpose I/O ports. Serial data input pin for UART channel 0. While UART channel 0 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O ports. Serial data output pin for UART channel 0. This function is enabled when UART channel 0 enables data output.
59
58
2
PPG1*4 P37
H
60
59
3
PPG0 P40
H
61
60
4
SIN0 P41
F
62
61
5
SOT0
F
10
MB90460 Series
(Continued) (Continued) Pin No.
QFPM06*2 63 LQFPSDIP*3 M09*1 62 6 Pin name P42 SCK0 P43 64 63 7 SNI0*4 P44 1 64 8 SNI1*4 P45 2 1 9 SNI2*4 P46 3 2 10 PPG2 P50 to P57 AN0 to AN7 AVCC AVR AVSS P60 15 14 22 SIN1 P61 16 15 23 SOT1 F F F F F F F I/O circuit General-purpose I/O ports. Serial clock I/O pin for UART channel 0. This function is enabled when UART channel 0 enables clock output. General-purpose I/O ports. Trigger input pins for position detection of the waveform sequencer. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P.*4 General-purpose I/O ports. Trigger input pins for position detection of the Multi-pulse generator. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P.*4 General-purpose I/O ports. Trigger input pins for position detection of the Multi-pulse generator. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P.*4 General-purpose I/O ports. Output pins for PPG channel 2. This function is enabled when PPG channel 2 enables output. General-purpose I/O ports. I A/D converter analog input pins. This function is enabled when the analog input specification is enabled. (ADER) . VCC power input pin for analog circuits. Reference voltage (+) input pin for the A/D converter. This voltage must not exceed VCC and AVCC. Reference voltage (-) is fixed to AVSS. VSS power input pin for analog circuits. General-purpose I/O ports. Serial data input pin for UART channel 1. While UART channel 1 is operating for input, the input of this pin is used as required and must not be used for any other in-put. General-purpose I/O ports. Serial data output pin for UART channel 1. This function is enabled when UART channel 1 enables data output. (Continued)
Function
4 to 11 3 to 10
11 to 18 19 20 21
12 13 14
11 12 13

11
MB90460 Series
(Continued) Pin No.
QFPM06*2 17 LQFPSDIP*3 M09*1 16 24
Pin name P62 SCK1 P63
I/O circuit General-purpose I/O port. F
Function
Serial clock I/O pin for UART channel 1. This function is enabled when UART channel 1 enables clock output. General-purpose I/O port. Usable as interrupt request input channel 7. Input is enabled when 1 is set in EN7 in standby mode. Input pin for operation mode specification. Connect this pin directly to VCC or VSS. Input pin for operation mode specification. Connect this pin directly to VCC or VSS. Power (0 V) input pin. Power (5 V) input pin. Capacity pin for power stabilization. Please connect to an approximately 0.1 F ceramic capacitor.
18
17
25
INT7 MD0 MD1, MD2 VSS VCC C
F
19 21, 22 25, 50 57 58
18 20, 21 24, 49 56 57
26 28, 29 32, 57 64 1
J J
*1 : FPT-64P-M09 *2 : FPT-64P-M06 *3 : DIP-64P-M01 *4 : MB90V460, MB90F462, MB90462 only. They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and waveform sequencer.
12
MB90460 Series
s I/O CIRCUIT TYPE
Classification
X1 N-ch P-ch X0 P-ch N-ch Xout
Type
Remarks
A
Main clock (main clock crystal oscillator) * At an oscillation feedback resistor of approximately 1 M
Standby mode control
B
R
* Hysteresis input * Pull-up resistor approximately 50 k
R
P-ch
Pull up control P-ch Pout
C
* CMOS output * Hysteresis input * Selectable pull-up resistor approximately 50 k * IOL = 4 mA * Standby control available
N-ch
Nout
Hysteresis input Standby mode control
R
P-ch
Pull up control P-ch Pout
D
* CMOS output * CMOS input * Selectable pull-up resistor approximately 50 k * Standby control available * IOL = 12 mA
N-ch
Nout
CMOS input Standby mode control
(Continued)
13
MB90460 Series
Classification
Type
Remarks * CMOS output * CMOS input * Selectable pull-up resistor approximately 50 k * Standby control available * IOL = 4 mA
R
P-ch
Pull up control P-ch Pout
E
N-ch
Nout
CMOS input Standby mode control
P-ch
Pout
N-ch
* * * *
CMOS output Hysteresis input Standby control available IOL = 4 mA
F
Nout
Hysteresis input Standby mode control
P-ch
Pout
N-ch
* * * *
CMOS output CMOS input Standby control available IOL = 12 mA
G
Nout
CMOS input Standby mode control
P-ch
Pout
N-ch
* * * *
CMOS output CMOS input Standby control available IOL = 4 mA
H
Nout
CMOS input Standby mode control
(Continued)
14
MB90460 Series
(Continued) Classification
Type * * * *
Remarks CMOS output CMOS input Analog input IOL = 4 mA
P-ch
Pout
N-ch
Nout
I
CMOS input Analog input control Analog input
* Hysteresis input J
15
MB90460 Series
s HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations : * When a voltage higher than VCC or lower than VSS is applied to input or output pins. * When a voltage exceeding the rating is applied between VCC and VSS. * When AVCC power is supplied prior to the VCC voltage. If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let it occur. For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage.
2. Handling unused input pins
Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 k resistance. Unused input/output pins may be left open in the output state, but if such pins are in the input state they should be handled in the same way as input pins.
3. Use of the external clock
When the device uses an external clock, drive only the X0 pin while leaving the X1 pin open (See the illustration below) .
MB90460 series X0 Open X1
4. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via the lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pins near the device.
5. Crystal Oscillator Circuit
Noise around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with the ground area for stabilizing the operation.
6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVSS, AVR) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage of AVR dose not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . 16
MB90460 Series
7. Connection of Unused Pins of A/D Converter
Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVR = VSS.
8. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
9. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more.
10. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again.
11. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state.
17
MB90460 Series
s BLOCK DIAGRAM
X0 X1 RST Clock control circuit Reset circuit (Watch-dog timer) Interrupt controller CPU F MC-16LX series core
2
Other pins VSS x 2, VCC x 1, MD0-2, C
Timebase timer Delayed interrupt generator Multi-functional Timer 16-bit PPG (Ch0) P37/PPG0
P11/INT1 P13/INT3 to P14/INT4 P40/SIN0 P41/SOT0 P42/SCK0 2 8 DTP/External interrupt
16-bit input capture (Ch0/1/2/3) UART (Ch0) Multi-pulse Generator 2 16-bit free-run timer 16-bit output compare (Ch0 to 5) F2MC-16LX Bus
4
4
P24/IN0 to P27/IN3
P17/FRCK P30/RTO0 (U) P31/RTO1 (X) P32/RTO2 (V) P33/RTO3 (Y) P34/RTO4 (W) P35/RTO5 (Z) P10/INT0/DTTI0
P36/PPG12 P15/INT5/TIN0 P16/INT6/TO0 P43/SNI02 to P45/SNI22 P00/OPT02 P01/OPT12 P02/OPT22 P03/OPT32 P04/OPT42 P05/OPT52 P12/INT2/DTTI12 P06/PWI02 P07/PWO02 P46/PPG2 3 3
16-bit PPG (Ch1)
1
16-bit reload timer (Ch0) 1 Waveform sequencer
Waveform generator
16-bit reload timer (Ch1) PWC (Ch1)
P20/TIN1 P21/TO1 P22/PWI1 P23/PWO1 P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7
PWC (Ch0) 16-bit PPG (Ch2) CMOS I/O port 0, 1, 3, 4 RAM ROM ROM correction ROM mirroring
1
UART (Ch1)
CMOS I/O port 1, 2, 3, 6 CMOS I/O port 5
A/D converter (8/10 bit)
8
P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7
AVCC AVR AVSS
Note : P00 to P07 (8 channels) : With registers that can be used as input pull-up resistors P10 to P17 (8 channels) : With registers that can be used as input pull-up resistors *1: Only MB90V460, MB90F462 and MB90462 have PWC (ch 0) , 16-bit PPG (ch 1) and waveform sequencer. They do not exist on MB90467. *2: The multi-pulse generator function can be used only by MB90V460, MB90F462 and MB90462. This function can not be used by MB90467. 18
MB90460 Series
s MEMORY MAP
FFFFFFH ROM area Address #1
FC0000H
010000H ROM area (FF bank image) Address #2 : Internal access memory : Access not allowed 004000H 003FE0H Address #3 RAM area 000100H 0000C0H 000000H Peripheral area In Single chip mode the mirror function is supported Register
Peripheral area
Parts No. MB90462/467 MB90F462 MB90V460
Address#1 FF0000H FF0000H (FF0000H)
Address#2 004000H 004000H 004000H
Address#3 000900H 000900H 002100H
Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H , the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH.
19
MB90460 Series
s I/O MAP
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH to 0FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH to 1FH CDCR1 RDR0 RDR1 CDCR0 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 ADER Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Analog input enable register PWCSL0 PWCSH0 PWC0 DIV0 Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Byte Word access access R/W R/W R/W R/W R/W R/W R/W Prohibited area PWC control status register CH0 PWC data buffer register CH0 Divide ratio control register CH0 R/W R/W R/W R/W R/W R/W R/W PWC timer (CH0) 00000000B 00000000B XXXXXXXXB XXXXXXXXB ------00B R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB -XXXXXXXB XXXXXXXXB ----XXXXB
Prohibited area R/W R/W R/W R/W R/W R/W R/W R/W Prohibited area Clock division control register 0 R/W R/W Communication prescaler 0 Communication prescaler 1 Port 0 Port 1 0---0000B R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 5, A/D 00000000B 00000000B 00000000B 00000000B -0000000B 00000000B ----0000B 11111111B
Prohibited area Clock division control register 1 Port 0 pull-up resistor setting register Port 1 pull-up resistor setting register R/W R/W R/W R/W R/W R/W 0---0000B 00000000B 00000000B
Prohibited area
(Continued)
20
MB90460 Series
Address 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH to 2FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH
Abbreviation SMR0 SCR0 SIDR0 / SODR0 SSR0 SMR1 SCR1 SIDR1 / SODR1 SSR1 PWCSL1 PWCSH1 PWC1 DIV1
Register Serial mode register 0 Serial control register 0 Input data register 0 / output data register 0 Serial status register 0 Serial mode register 1 Serial control register 1 Input data register 1 / output data register 1 Status register 1 PWC control status register CH1 PWC data buffer register CH1 Divide ratio control register CH1
Byte Word access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value 00000000B 00000100B
UART0
XXXXXXXXB 00001000B 00000000B 00000100B
UART1
XXXXXXXXB 00001000B 00000000B 00000000B
PWC timer (CH1)
XXXXXXXXB XXXXXXXXB ------00B
Prohibited area ENIR EIRR ELVRL ELVRH ADCS0 ADCS1 ADCR0 ADCR1 PDCR0 PCSR0 PDUT0 PCNTL0 PCNTH0 Interrupt / DTP enable register Interrupt / DTP cause register Request level setting register (Lower Byte) Request level setting register (Higher Byte) A/D control status register 0 A/D control status register 1 A/D data register 0 A/D data register 1 PPG0 down counter register PPG0 period setting register PPG0 duty setting register PPG0 control status register R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R W W R/W R/W 8/10-bit A/D converter DTP/external interrupt 00000000B XXXXXXXXB 00000000B 00000000B 00000000B 00000000B XXXXXXXXB 00000-XXB 11111111B 11111111B XXXXXXXXB 16-bit PPG timer (CH0) XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B
(Continued)
21
MB90460 Series
Address 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH
Abbreviation PDCR1 PCSR1 PDUT1 PCNTL1 PCNTH1 PDCR2 PCSR2 PDUT2 PCNTL2 PCNTH2 TMRR0 TMRR1 TMRR2 DTCR0 DTCR1 DTCR2 SIGCR
Register PPG1 down counter register PPG1 period setting register PPG1 duty setting register PPG1 control status register PPG2 down counter register PPG2 period setting register PPG2 duty setting register PPG2 control status register 16-bit timer register 0 16-bit timer register 1 16-bit timer register 2 16-bit timer control register 0 16-bit timer control register 1 16-bit timer control register 2 Waveform control register
Byte Word access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W W R/W R/W R W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value 11111111B 11111111B XXXXXXXXB
16-bit PPG timer (CH1)
XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B 11111111B 11111111B XXXXXXXXB
16-bit PPG timer (CH2)
XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B
Waveform generator
CPCLRB / Compare clear buffer register / CPCLR Compare clear register (lower) TCDT TCCSL TCCSH Timer data register (lower) Timer control status register (lower) Timer control status register (upper)
16-bit free-running timer
00000000B 00000000B 00000000B -0000000B
(Continued)
22
MB90460 Series
Address 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH to 6EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH
Abbreviation IPCP0 IPCP1 IPCP2 IPCP3 PICSL01 PICSH01 ICSL23 ICSH23
Register Input capture data register CH0 Input capture data register CH1 Input capture data register CH2 Input capture data register CH3 PPG output control / Input capture control status register 01 (lower) PPG output control / Input capture control status register 01 (upper) Input capture control status register 23 (lower) Input capture control status register 23 (upper)
Byte Word access access R/W R/W R/W R R R R R R/W R/W R/W R
Resource name
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B ------00B
16-bit input capture (CH0 to CH3)
Prohibited area ROMM ROM mirroring function selection register W W R/W R/W R/W R/W R/W R/W ROM mirroring function -------1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Output compare XXXXXXXXB (CH0 to CH5) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
OCCPB0/ Output compare buffer register / OCCP0 output compare register 0 OCCPB1/ Output compare buffer register / OCCP1 output compare register 1 OCCPB2/ Output compare buffer register / OCCP2 output compare register 2 OCCPB3/ Output compare buffer register / OCCP3 output compare register 3 OCCPB4/ Output compare buffer register / OCCP4 output compare register 4 OCCPB5/ Output compare buffer register / OCCP5 output compare register 5
(Continued)
23
MB90460 Series
Address 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 000090H to 9DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H to A7H 0000A8H 0000A9H
Abbreviation OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 TMCSRL0 TMCSRH0 TMR0 / TMRD0 TMCSRL1 TMCSRH1 TMR1 / TMRD1 OPCLR OPCUR IPCLR IPCUR TCSR NCCR
Register Compare control register 0 Compare control register 1 Compare control register 2 Compare control register 3 Compare control register 4 Compare control register 5 Timer control status register CH0 (lower) Timer control status register CH0 (upper) 16 bit timer register CH0 / 16-bit reload register CH0 Timer control status register CH1 (lower) Timer control status register CH1 (upper) 16 bit timer register CH1 / 16-bit reload register CH1 Output control lower register Output control upper register Input control lower register Input control upper register Timer control status register Noise cancellation control register
Byte Word access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value 00000000B -0000000B 00000000B -0000000B 00000000B -0000000B 00000000B
Output compare (CH0 to CH5)
16-bit reload timer (CH0)
----0000B XXXXXXXXB XXXXXXXXB 00000000B
16-bit reload timer (CH1)
----0000B XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B
Waveform sequencer
Prohibited area PACSR DIRR LPMCR CKSCR Program address detect control status register Delayed interrupt cause / clear register Low-power consumption mode register Clock selection register R/W R/W R/W R/W Prohibited area WDTC TBTC Watchdog control register Timebase timer control register R/W R/W R/W R/W Watchdog timer Timebase timer X-XXX111B 1--00100B R/W R/W R/W R/W Rom correction Delayed interrupt Low-power consumption control register 00000000B -------0B 00011000B 11111100B
(Continued)
24
MB90460 Series
Address 0000AAH to ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to FFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H
Abbreviation
Register
Byte Word access access Prohibited area
Resource name
Initial value
FMCS
Flash memory control status register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15
R/W Prohibited area
R/W
Flash memory interface circuit
00010000B
ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W External area
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller
00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B
PADR0L PADR0M PADR0H PADR1L PADR1M PADR1H
Program address detection register 0 (Lower Byte) Program address detection register 0 (Middle Byte) Program address detection register 0 (Higher Byte) Program address detection register 1 (Lower Byte) Program address detection register 1 (Middle Byte) Program address detection register 1 (Higher Byte)
R/W R/W R/W R/W R/W R/W
R/W R/W R/W Rom correction R/W R/W R/W
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
25
MB90460 Series
(Continued)
Address 003FE0H 003FE1H 003FE2H 003FE3H 003FE4H 003FE5H 003FE6H 003FE7H 003F78H 003FE9H 003FEAH 003FEBH 003FECH 003FEDH 003FEEH 003FEFH 003FF0H 003FF1H 003FF2H 003FF3H 003FF4H 003FF5H 003FF6H 003FF7H 003FF8H 003FF9H 003FFAH 003FFBH 003FFCH 003FFDH 003FFEH to 003FFFH Abbreviation OPDBR0 OPDBR1 OPDBR2 OPDBR3 OPDBR4 OPDBR5 OPEBR6 OPEBR7 OPEBR8 OPEBR9 OPEBRA OPEBRB OPDR CPCR TMBR Register Output data buffer register 0 Output data buffer register 1 Output data buffer register 2 Output data buffer register 3 Output data buffer register 4 Output data buffer register 5 Output data buffer register 6 Output data buffer register 7 Output data buffer register 8 Output data buffer register 9 Output data buffer register A Output data buffer register B Output data register Compare clear register Timer buffer register Byte Word access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R Waveform sequencer Resource name Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B XXXXXXXXB 0000XXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B
Prohibited area
26
MB90460 Series
* Meaning of abbreviations used for reading and writing R/W : Read and write enabled R : Read only W : Write only * Explanation of initial values 0 : The bit is initialized to 0. 1 : The bit is initialized to 1. X : The initial value of the bit is undefined. : The bit is not used. Its initial value is undefined. The Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003FE0H to 003FFFH. Note : For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However, initial value for resets that initializes the value is listed.
27
MB90460 Series
s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause Reset INT9 instruction Exception processing A/D converter conversion termination Output compare channel 0 match End of measurement by PWC0 timer / PWC0 timer overflow 16-bit PPG timer 0 Output compare channel 1 match 16-bit PPG timer 1 Output compare channel 2 match 16-bit reload timer 1 underflow Output compare channel 3 match DTP/ext. interrupt channels 0/1 detection DTTI0 Output compare channel 4 match DTP/ext. interrupt channels 2/3 detection DTTI1 Output compare channel 5 match End of measurement by PWC1 timer / PWC1 timer overflow DTP/ext. interrupt channels 4/5 detection Waveform sequencer timer compare match / write timing DTP/ext. interrupt channels 6/7 detection Waveform sequencer position detect / compare interrupt Waveform generator 16-bit timer 0/1/2 underflow 16-bit reload timer 0 underflow 16-bit free-running timer zero detect 16-bit PPG timer 2 Input capture channels 0/1 16-bit free-running timer compare clear EI2OS support x x x Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H ICR10 0000BAH*1 ICR11 0000BBH*1 ICR08 0000B8H*1 ICR07 0000B7H*1 ICR06 0000B6H*1 ICR05 0000B5H*2 ICR04 0000B4H*1 ICR02 0000B2H*1 ICR03 0000B3H*1 Interrupt control register ICR Address High Priority
*2
ICR00 0000B0H*1
ICR01 0000B1H*1
ICR09 0000B9H*1
(Continued)
28
MB90460 Series
(Continued)
Interrupt cause Input capture channels 2/3 Timebase timer UART1 receive UART1 send UART0 receive UART0 send Flash memory status Delayed interrupt generator module EI2OS support Interrupt vector Number #35 #36 #37 #38 #39 #40 #41 #42 23H 24H 25H 26H 27H 28H 29H 2AH Address FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register ICR Address Priority
*2
ICR12 0000BCH*1 ICR13 0000BDH*1 ICR14 0000BEH*1 ICR15 0000BFH*1
Low
: Can be used and support the EI2OS stop request. : Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal. x : Cannot be used. : Usable when an interrupt cause that shares the ICR is not used.
29
MB90460 Series
s PERIPHERAL RESOURCES
1. Low-Power Consumption Control Circuit
The MB90460 series has the following CPU operating mode configured by selection of an operating clock and clock operation control. * Clock mode PLL clock mode : A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the CPU and peripheral functions. Main clock mode : The main clock, with a frequency one-half that of the oscillation clock (HCLK) , is used to operate the CPU and peripheral functions. In main clock mode, the PLL multiplier circuit is inactive. * CPU intermittent operation mode CPU intermittent operation mode causes the CPU to operate intermittently, while high-speed clock pulses are supplied to peripheral functions, reducing power consumption. In CPU intermittent operation mode, intermittent clock pulses are only applied to the CPU when it is accessing a register, internal memory, a peripheral function, or an external unit. * Standby mode In standby mode, the low power consumption control circuit stops supplying the clock to the CPU (sleep mode) or the CPU and peripheral functions (timebase timer mode) , or stops the oscillation clock itself (stop mode) , reducing power consumption. * PLL sleep mode PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock mode; other components continue to operate on the PLL clock. * Main sleep mode Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock mode; other components continue to operate on the main clock. * PLL timebase timer mode PLL timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, PLL clock and timebase timer, to stop. All functions other than the timebase timer are deactivated. * Main timebase timer mode Main timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, main clock and the timebase timer, to stop. All functions other than the timebase timer are deactivated. * Stop mode Stop mode causes the source oscillation to stop. All functions are deactivated.
30
MB90460 Series
Block Diagram
Low power mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 RESV Pin high impedance control circuit RST Pin CPU intermittent operation selecter Release reset RST 3 Standby control circuit Internal reset generation circuit Pin Hi-z control
Internal reset
Select intermittent cycles CPU clock control circuit CPU clock
Stop and sleep signals Stop signal Peripheral clock control circuit Peripheral clock
Cancel interrupt
Machine clock Clock generator Clock selector 2
Oscillation stabilization wait is passed
Oscillation stabilization wait interval selector 2
x1 x2 x3 x4 PLL multipiler circuit
RESV MCM WS1 WS0 RESV MCS CS1 CS0 Clock selection register (CKSCR)
X0 Pin X1 Pin
Divideby-2 Main clock System clock generation circuit
Divideby-512
Divideby-2
Divideby-4
Divideby-4
Divideby-4
Timebase timer
31
MB90460 Series
2. I/O Ports
(1) Outline of I/O ports When a data register serving for control output is read, the data output from it as a control output is read regardless of the value in the direction register. Note that, if a read-modify-write instruction (such as a bit set instruction) is used to preset output data in the data register when changing its setting from input to output, the data read is not the data register latched value but the input data from the pin. Ports 0 to 4 and 6 are input/output ports which serve as inputs when the direction register value is "0" or as outputs when the value is "1". Port 5 are input/output ports as other port when ADER is 00H. Block Diagram * Block diagram of Port 0 pins
RDR Port data register (PDR)
Resource output Direct resource input Resource output enable Pull-up resistor About 50 K
PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) DDR read Pin
Internal data bus
(Continued)
32
MB90460 Series
* Block diagram of Port 1 pins
RDR Port data register (PDR)
Resource output Resource input Resource output enable Pull-up resistor About 50 K
PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) Pin
* Block diagram of Port 2 pins
Internal data bus Internal data bus
DDR read
Port data register (PDR)
Resource output Resource input Resource output enable
PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) Pin
DDR read
(Continued)
33
MB90460 Series
* Block diagram of Port 3 pins
Port data register (PDR)
Resource output Resource output enable
PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) Pin
* Block diagram of Port 4 pins
Internal data bus Internal data bus
DDR read
Port data register (PDR)
Resource output Resource input Resource output enable
PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) Pin
DDR read
(Continued)
34
MB90460 Series
(Continued) * Block diagram of Port 5 pins
ADER Port data register (PDR) Analog input
PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) DDR read Pin
* Block diagram of Port 6 pins
Internal data bus Internal data bus
Port data register (PDR)
Resource output Resource input Resource output enable
PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) External interrupt enable Pin
DDR read
35
MB90460 Series
3. Timebase Timer
The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization to the internal count clock (main oscillator clock divided by 2) . Features of timebase timer : * Interrupt generated when counter overflow * EI2OS supported * Interval timer function : An interrupt generated at four different time intervals * Clock supply function : Four different clocks can be selected as a watchdog timer's count clock Supply clock for oscillation stabilization
Block Diagram
Timebase timer counter Divide-by -two HCLK x 21 x 22 x 23
To watchdog timer
x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218
OF Counter clear
OF
OF
OF To the oscillation setting time selector in the clock control section
Power-on reset Stop mode start CKSCR : MCS = 1 to 0 *1 TBOF clear Timebase timer interrupt signal #36 (24H)*2 Timebase timer interrpt register (TBTC) TBIE TBOF TBR TBC1 TBC0 Counter clear circuit Interval timer selector TBOF set
OF : Overflow HCLK : Oscillation clock *1 : Switching of the machine clock from the oscillation clock to the PLL clock *2 : Interrupt number
36
MB90460 Series
4. Watchdog Timer
The watchdog timer is a 2-bit counter that uses the timebase timer's supply clock as the count clock. After activation, if the watchdog timer is not cleared within a given period, the CPU will be reset. * Features of Watchdog Timer : Reset CPU at four different time intervals Status bits to indicate the reset causes
Block Diagram
Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0
Watchdog timer
2 Activation with CLR CLR Overflow Watchdog reset generator To the internal reset generator
Start of sleep mode Start of hold status mode Start of stop mode
Counter clear control circuit
Count clock selector CLR
2-bit counter
Clear
4
(Timebase timer counter) One-half of HCLK x 21 x 2 2 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218
HCLK : Oscillation clock
37
MB90460 Series
5. 16 bit reload timer ( x 2)
The 16-bit reload timer provides two operating mode, internal clock mode and event count mode. In each operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot mode) . Output pins TO1 - TO0 are able to output different waveform accroding to the counter operating mode. TO1 TO0 toggles when counter underflow if counter is operated as reload mode. TO1 - TO0 output specified level (H or L) when counter is counting if the counter is in one-shot mode. Features of the 16 bit reload timer : * Interrupt generated when timer underflow * EI2OS supported * Internal clock operating mode : Three internal count clocks can be selected Counter can be activated by software or exteranl trigger (singal at TIN1 - TIN0 pin) Counter can be reloaded or stopped when underflow after activated * Event count operating mode : Counter counts down by one when specified edge at TIN1 - TIN0 pin Counter can be reloaded or stopped when underflow
38
MB90460 Series
Block Diagram
F2MC-16LX Bus TMRD0*1 16-bit reload register Reload signal TMR0*1 16-bit timer register Count clock generation circuit CLK Gate input Reload control circuit
Machine clock
Prescaler Clear
3
Valid clock judgment circuit CLK
Wait signal To UART0 and UART1 *1 Pin EN P16/TO0*1
Internal clock Pin P15/TIN0*1 Input control circuit External clock 3 Function selection 2 Select signal Clock selector
Output control circuit Output signal generation circuit Invert
Operation control circuit

CSL1 CSL0 MOD2 MOD1MOD0OUTE OUTL RELD INTE
UF CNTE TRG Interrupt request signal #30 (1EH)*2 <#32 (20H)>
Timer control status register (TMCSR0)*1
*1 : This register includes channel 0 and channel 1. The register enclosed in < and > indicates the channel 1 register. *2 : Interrupt number
39
MB90460 Series
6. 16-bit PPG Timer ( x 3 )
The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting buffer register, 16-bit duty setting buffer register, 16-bit control register and a PPG output pin. This module can be used to output pulses synchronized by software trigger or GATE signal from Multi-functional timer, refer to "Multi-functional Timer" Features of 16-bit PPG Timer : * Two operating mode : PWM and One-shot * 8 types of counter operation clock (, /2, /4, /8, /16, /32, /64, /128) can be selected * Interrupt generated when trigger signal arrived, or counter borrow, or change of PPG output * EI2OS supported
Block Diagram
Period Setting Buffer Register 0/1/2 Prescaler CKS2 CKS1 CKS0 Period Setting Register 0/1/2
Duty Setting Buffer Register 0/1/2 Duty Setting Register 0/1/2
1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 F2MC-16LX Bus Machine clock
LOAD 16-bit down counter STOP START BORROW
CLK
Comparator
MDSE PGMS OSEL POEN
P37/PPG0 or P36/PPG1 or P46/PPG2 Pin
S Down Counter Register 0/1/2 R
Q PPG0 (multi-functional timer) or PPG1 (multi-pulse generator) or PPG2
Interrupt selection GATE-from multi-functional timer (for PPG ch. 0 only) Edge detection
Interrupt #14/#16/#32
IRS1 IRS0 IRQF IREN
(for PPG ch. 1 & 2) STGR CNTE RTRG
40
MB90460 Series
7. Multi-functional Timer
The 16-bit multi-functional timer module consists of one 16-bit free-running timer, four input capture circuits, six output comparators and one channel of 16-bit PPG timer. This module allows six independent waveforms generated by PPG timer or waveform generator to be outputted. With the 16-bit free-run timer and the input capture circuit, a input pulse width measurement and external clock cycle measurement can be done. (1) 16-bit free-running timer (1 channel) * The 16-bit free-running timer consists of a 16-bit up/up-down counter, control register, 16-bit compare clear register (with buffer register) and a prescaler. * 8 types of counter operation clock (, /2, /4, /8, /16, /32, /64, /128) can be selected. ( is the machine clock) * Two types of interrupt causes : - Compare clear interrupt is generated when there is a comparing match with compare clear register and 16bit free-run timer. - Zero detection interrupt is generated while 16-bit free-running timer is detected as zero in count value. * EI2OS supported * The compare clear register has a selectable buffer register, into which data is written for transfer to the compare clear register. When the timer is stopped, transfer occurs immediately when the data is written to the buffer. When the timer is operation, data transfer from the buffer occurs when the timer value is detected to be zero. * Reset, software clear, compare match with compare clear register in up-count mode will reset the counter value to "0000H". * Supply clock to output compare module : The prescaler ouptut is acted as the count clock of the output compare. (2) Output compare module (6 channels) * The output compare module consists of six 16-bit compare registers (with selectable buffer register) , compare output latch and compare control registers. An interrupt is generated and output level is inverted when the value of 16-bit free-running timer and compare register are matched. * 6 compare registers can be operated independently. * Output pins and interrupt flag are corresponding to each compare register. * Inverts output pins by using 2 compare registers together. 2 compare registers can be paired to control the output pins. * Setting the initial value for each output pin is possible. * Interrupt generated when there is a comparing match with output compare register and 16 bit free-run timer * EI2OS supported (3) Input capture module (4 channels) Input capture consists of 4 independent external input pins, the corresponding capture register and capture control register. By detecting any edge of the input signal from the external pin, the value of the 16-bit freerunning timer can be stored in the capture register and an interrupt is generated simultaneously. * Operation synchronized with the 16-bit free-run timer's count clock. * 3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal can be selected and there is indication bit to show the trigger edge is rising or falling. * 4 input captures can be operated independently. * Two independent interrupts are generated when detecting a valid edge from external input. * EI2OS supported (4) 16-bit PPG timer ( x 1) The 16-bit PPG timer 0 is used to provide a PPG signal for waveform generator.
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MB90460 Series
(5) Waveform Generator module The waveform generator consists of three 16-bit timer registers, three timer control registers and 16-bit waveform control register. With waveform generator, it is possible to generate real time output, 16-bit PPG waveform output, non-overlap 3-phase waveform output for inverter control and DC chopper waveform output. * It is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer. (Dead-time timer function) * It is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel mode. (Dead-time timer function) * By detecting realtime output compare match, GATE signal of the PPG timer operation will be generated to start or stop PPG timer operation. (GATE function) * When a match is detected by realtime output compare, the 16-bit timer is activated. The PPG timer can be started or stopped easily by generating a GATE signal for PPG operation until the 16-bit timer stops. (GATE function) * Forced to stop output waveform using DTTI0 pin input * Interrupt generated when DTTI0 active or 16-bit tmer underflow * EI2OS supported * MCU to 3-phase Motor Interface Circuit
VCC
RTO0(U)
RTO2(V) (U)
RTO4(W) (V) RTO5(Z) (W)
RTO1(X)
RTO3(Y)
RTO0 (U) , RTO2 (V) , RTO4 (W) are called "UPPER ARM". RTO1 (X) , RTO3 (Y) , RTO5 (Z) are called "LOWER ARM". RTO0 (U) and RTO1 (X) are called "non-overlapping output pair". RTO2 (V) and RTO3 (Y) are called "non-overlapping output pair". RTO4 (W) and RTO5 (Z) are called "non-overlapping output pair". (U) , (V) , (W) are the 3-phase coil connection.
42
MB90460 Series
* 3-phase Motor Coil Connection Circuit
(U)
Star Connection Circuit
(W)
(V)
(U)
Delta Connection Circuit
(W)
(V)
43
MB90460 Series
Block Diagram * Block Diagram of Multi-functional Timer
Real time I/O RTO0 Interrupt#12 Interrupt#15 Interrupt#17 Interrupt#19 Interrupt#21 Interrupt#23 16-bit Output Compare RT0 to 5 output compare 0 output compare 1 output compare 2 output compare 3 output compare 4 output compare 5 RT0 to 5 Waveform generator buffer transfer counter value RTO4 RTO5 DTTI Interrupt#31 Interrupt#34 F2MC-16LX Bus 16-bit free- A/D trigger running timer Zero detect Compare clear A/D trigger Interrupt#29 Interrupt#20 PPG0 GATE Pin P34/RTO4 (W) Pin P35/RTO5 (Z) Pin P10/INT0/DTTI0 16-bit timer 0/1/2 underflow DTTI0 falling edge detect PPG0 GATE RTO1 RTO2 RTO3 Pin P30/RTO0 (U) Pin P31/RTO1 (X) Pin P32/RTO2 (V) Pin P33/RTO3 (Y)
EXCK
Pin P17/FRCK
counter Interrupt #33 value Interrupt #35 IN0 16-bit Input Capture IN1 IN2 IN3
Input capture 0/1 Input capture 2/3 Pin P24/IN0 Pin P25/IN1 Pin P26/IN2 Pin P27/IN3
(Continued)
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MB90460 Series
* Block diagram of 16-bit free-running timer
STOP MODE SCLR CLK2 CLK1 CLK0 Prescaler
CLR STOP UP/ UP-DOWN 16-bit free-running timer CK
Zero detect circuit
Zero detect (to output compare)
To Input Capture & Output Compare transfer 16-bit compare clear register Compare circuit Compare clear match (to output compare)
F2MC-16LX BUS
16-bit compare clear buffer register
I0 O I1 Selector
Interrupt #31 (1FH)
Mask Circuit
Selector I1 O I0 MSI2 MSI1 MSI0 ICLR
I0 O I1 Selector
Interrupt #34 (22H) A/D trigger
ICRE IRQZF IRQZE I0 O I1 Selector
(Continued)
45
MB90460 Series
* Block diagram of 16-bit output compare
Count value from Free-running timer BUF0 BTS0 I0 O I1 Selector BUF1 Compare circuit Compare buffer register 1/3/5 transfer Compare register 1/3/5 I0 O I1 Selector T Q RT0/2/4 (Waveform generator) RT1/3/5 (Waveform generator) Interrupt #12, #17, #21 #15, #19, #23 BTS1 Zero detect from free-running timer Compare clear match from free-running timer
Compare buffer register 0/2/4 transfer Compare register 0/2/4 F2MC-16LX BUS
CMOD
Compare circuit
T IOP1 IOP0 IOE1 IOE0
Q
* Block diagram of 16-bit input capture
Count value from Free-running timer
Capture register 0/2
Edge detect
IN0/2
F2MC-16LX BUS
EG11 EG10 EG01 EG00
IEI1
IEI0
Capture register 1/3
Edge detect
IN1/3
ICP0
ICP1
ICE0
ICE1 Interrupt #33, #35 #33, #35
(Continued)
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MB90460 Series
(Continued) * Block diagram of waveform generator
Divider
DCK2
DCK1
DCK0
NRSL
DTIF
DTIE
NWS1 NWS0
SIGCR
DTTI0 control circuit PICSH01 PGEN1 PGEN0
Noise Cancellation
DTTI0
DTCR0 TMD2 TMD1 TMD0 GTEN1 GTEN0 TO0 RT0 RT1 Waveform control
GATE 0/1 GATE (to PPG0) Output Control Output Control Output Control
TO1 Selector 16-bit timer 0 Compare circuit Selector U 16-bit timer register 0 Dead time generator X GATE 2/3 TO2 Waveform control TO3
RTO0 (U)
RTO1 (X)
DTCR1 TMD2 TMD1 TMD0 GTEN1 GTEN0 F2MC-16LX BUS PICSH01 PGEN3 PGEN2 RT2 RT3
Selector 16-bit timer 1 Compare circuit Selector V 16-bit timer register 1 DTCR2 TMD2 TMD1 TMD0 GTEN1 GTEN0 PICSH01 PGEN5 PGEN4 RT4 RT5 Selector 16-bit timer 2 Compare circuit Selector W 16-bit timer register 2 Dead time generator Z Waveform control TO5 TO4 Dead time generator Y GATE 4/5
RTO2 (V)
RTO3 (Y)
RTO4 (W)
RTO5 (Z)
PPG0
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MB90460 Series
8. Multi-Pulse Generator
The Multi-pulse Generator consists of a 16-bit PPG timer, a 16-bit reload timer and a waveform sequencer. By using the waveform sequencer, 16-bit PPG timer output signal can be directed to Multi-pulse Generator output (OPT5 to 0) according to the input signal of Multi-pulse Generator (SNI2 to 0) . Meanwhile, the OPT5 to 0 output signal can be hardware terminated by DTTI input (DTTI1) in case of emergency. The OPT5 to 0 output signals are synchronized with the PPG signal in order to eliminate the unwanted glitch. The Multi-pulse generator has the following features : * Output Signal Control - 12 output data buffer registers are provided - Output data register can be updated by any one of output data buffer registers when : 1. an effective edge detected at SNI2 - SNI0 pin 2. 16-bit reload timer underflow 3. output data buffer register OPDBR0 is written * Output data register (OPDR) determines which OPT terminals (OPT5 - 0) output the 16-bit PPG waveform - Waveform sequencer is provided with a 16-bit timer to measure the speed of motor - The 16-bit timer can be used to disable the OPT output when the position detection is missing * Input Position Detect Control - SNI2 - SNI0 input can be used to detect the rotor position - A controllable noise filter is provided to the SNI2 - SNI0 input * PPG Synchronization for Output signal - OPT output is able to synchronize the edge of PPG waveform to avoid a short pulse (or glitch) appearance * Vaious interrupt generation causes * EI2OS supported
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MB90460 Series
Block Diagram * Block diagram of Multi-pulse generator
P12/INT2/DTTI1 Pin P45/SNI2 Pin
DTTI SNI2
OPT5 OPT4
Pin Pin
P05/OPT5 P04/OPT4
P44/SNI1
Pin
SNI1
OPT3 OPT2 OPT1 OPT0 WAVEFORM SEQUENCER
Pin
P03/OPT3 P02/OPT2 P01/OPT1 P00/OPT0
P43/SNI0 F2MC-16LX Bus
Pin
SNI0
Pin Pin Pin
P15/INT5/TIN0 Pin
TIN0
16-BIT PPG TIMER 1
PPG1
PPG1
Interrupt #22 Interrupt #26
INTERRUPT #22 INTERRUPT #26
16-BIT RELOAD TIMER 0
TOUT TIN
WIN0 TIN0O Interrupt #28 INTERRUPT #28
Pin
P16/INT6/TO0
(Continued)
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MB90460 Series
(Continued) * Block diagram of waveform sequencer
WRITE TIMING INTERRUPT Interrupt #22 OPCR Register POSITION DETECTION INTERRUPT PDIRT Interrupt #26
DTIE DTIF NRSL OPS2 OPS1 OPS0 WTIF WTIE PDIF PDIE OPE5 OPE4 OPE3 OPE2 OPE1 OPE0 From PPG1 WTS1 WTS0 Pin OPDR Register OUTPUT CONTROL CIRCUIT OP x 1/OP x 0 Pin Pin Pin Pin Pin DTTI1 Control Circuit Noise Filter P00/OPT0 P01/OPT1 P02/OPT2 P03/OPT3 P04/OPT4 P05/OPT5
SYN Circuit OPDBRB to 0 Registers
OUTPUT DATA BUFFER REGISTER x 12
P12/INT2/DTTI1 Pin D1 D0
DECODER
3
RDA2 to 0
3 COMPARE CLEAR INTERRUPT
F2MC-16LX Bus
BNKF
Pin
P15/INT5/TIN0
16-BIT TIMER
WTO CCIRT WTIN1
P43/SNI0 Pin WTO POSITION DETECT CIRCUIT
DATA WRITE CONTROL UNIT OPS2 OPS1 OPS0 3 SELECTOR
P44/SNI1 Pin P45/SNI2 Pin
TIN0O TIN0O
WTIN0 WTIN0
WTIN1
WTIN1
COMPARISON CIRCUIT
WTS1 WTS0 CPIF CPIE CPD2 CPD1 CPD0 CMPE CPE1 CPE0 SNC2 SNC1 SNC0 SEE2 SEE1 SEE0 IPCR Register COMPARE MATCH INTERRUPT
S21
S20
S11
S10
S01
S00
D1
D0
NCCR Register
PDIRT
Interrupt #28
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MB90460 Series
9. PWC Timer
The PWC (pulse width count) timer is a 16-bit multi-function up-counter with reload timer functions and inputsignal pulse-width count functions as well. The PWC timer consists of a 16-bit counter, on input pulse divider, a divide ratio control register, a count input pin, a pulse output pin, and a 16-bit control register. The PWC timer has the following features : * Interrupt generated when timer overflow or end of PWC measurement. * EI2OS supported * Timer functions : - Generates an interrupt request at set time intervals. - Outputs pulse signals synchronized with the timer cycle. - Selects the counter clock from among three internal clocks. * Pulse-width count functions - Counts the time between external pulse input events. - Selects the counter clock from among three internal clocks. - Count mode * H pulse width (rising edge to falling edge) /L pulse width (falling edge to rising edge) * Rising-edge cycle (rising edge to falling edge) /Falling-edge cycle (falling edge to rising edge) * Count between edges (rising or falling edge to falling or rising edge) Capable of counting cycles by dividing input pulses by 22, 24, 26, 28 using an 8-bit input divider. Generates an interrupt request upon the completion of count operation. Selects single or consecutive count operation.
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MB90460 Series
Block Diagram
PWC read 16 16
Error detection PWC 16 Reload
ERR
Overflow
F.F.
P07/PWO0 P23/PWO1
Write enabled
Data transfer Overflow
16 Clock 22 23 Count enabled CKS1, CKS0, Divider clear Internal clock (machine clock / 4) P06/PWI0 P22/PWI1 Clock divider
16-bit up count timer Timer clear
F2MC-16LX bus
Control circuit Flag setting Start edge selection Count end edge End edge selection Edge detection Divider ON/OFF
Count bit output
Count start edge 8-bit divider Count end interrupt request Overflow interrupt request 15 PWCS 2 CKS0 ERR CKS1 Division rate selection DIVR
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MB90460 Series
10. UART
The UART is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication. The UART has the following features : * Full-duplex double buffering * Capable of asynchronous (start-stop bit) and CLK-synchronous communications * Support for the multiprocessor mode * Various method of baud rate generation : - External clock input possible - Internal clock (a clock supplied from 16-bit reload timer can be used.) - Embedded dedicated baud rate generator Operation Baud rate Asynchronous CLK synchronous 31250/9615/4808/2404/1202 bps 2 M/1 M/500 K/250 K/125 K/62.5 Kbps
* : Assuming internal machine clock frequencies of 6, 8, 10, 12, and 16 MHz * Error detection functions (parity, framing, overrun) * NRZ (Non Return to Zero) Signal format * Interrupt request : - Receive interrupt (receive complete, receive error detection) - Transmit interrupt (transmission complete) - Transmit / receive conforms to extended intelligent I/O service (EI2OS) * Flexible data length : - 7 bit to 9 bit selective (without a parity bit) - 6 bit to 8 bit selective (with a parity bit)
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MB90460 Series
Block Diagram
Control bus Reception interrupt request output Dedicated baud rate generator 16-bit reload timer Pin SCK0, 1 Start bit detection circuit Reception bit counter Reception parity counter Send start circuit Send interrupt request output Clock selector Reception clock Reception control circuit Send clock send control circuit
Send bit counter
Send parity counter
Pin SOT0, 1 Start of transmission EI2OS receive error generation signal (to CPU) PE ORE FRE RDRF TDRE BDS RIE TIE
Pin SIN0, 1
Reception shift register
End of reception
Send shift register
Reception status determination circuit
Serial input data register (0, 1)
Serial output data register (0, 1)
Internal data bus
Communication prescaler control register
MD
Serial mode register 0, 1
DIV2 DIV1 DIV0
MD1 MD0 CS2 CS1 CS0 RST SCKE SOE
Serial control register 0, 1
PEN P SBL CL A/D REC RXE TXE
Serial status register 0, 1
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MB90460 Series
11. DTP/External Interrupts
The DTP/external interrupt circuit is activated by the signal supplied to a DTP/external interrupt pin. The CPU accepts the signal using the same procedure it uses for normal hardware interrupts and generates external interrupts or activates the extended intelligent I/O service (EI2OS) . Features of DTP/External Interrupt : * Total 8 external interrupt channels * Two request levels ("H" and "L") are provided for the intelligent I/O service. * Four request levels (rising edge, falling edge, "H" level and "L" level) are provided for external interrupt requests.
Block Diagram
Request level setting register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 2 Pin P63/INT7 Pin P16/INT6/TO0 Pin P15/INT5/TIN0 Pin P14/INT4 Selector Selector Internal data bus Selector Selector Selector Selector Selector 2 2 2 2 2 2 2 Selector Pin
P10/INT0/DTTI0 Pin P11/INT1 Pin P12/INT2/DTTI1 Pin P13/INT3
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Interrupt request number #20(14H) #22(16H) #25(19H) #27(1BH)
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
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MB90460 Series
12. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate a task switching interrupt. Interrupt requests to the F2MC-16LX CPU can be generated and cleared by software using this module. Block Diagram
F2MC- 16LX bus
Delayed interrupt cause issuance/cancellation decoder
Interrupt cause latch
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MB90460 Series
13. A/D Converter
The converter converts the analog voltage input to an analog input pin (input voltage) to a digital value. The converter has the following features : * The minimum conversion time is 6.13 s (for a machine clock of 16 MHz; includes the sampling time) . * The minimum sampling time is 2.0 s (for a machine clock of 16 MHz) . * The converter uses the RC-type successive approximation conversion method with a sample hold circuit. * A resolution of 10 bits or 8 bits can be selected. * Up to eight channels for analog input pins can be selected by a program. * Various conversion mode : - Single conversion mode : Selectively convert one channel. - Scan conversion mode : Continuously convert multiple channels. Maximum of 8 program selectable channels. - Continuous conversion mode : Repeatedly convert specified channels. - Stop conversion mode : Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.) * At the end of A/D conversion, an interrupt request can be generated and EI2OS can be activated. * In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being lost through continuous conversion. * The conversion can be activated by software, 16-bit reload timer 1 (rising edge) and 16-bit free-running timer zero detection edge.
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MB90460 Series
Block Diagram
AVCC
AVR
AVSS
MPX D/A converter
Sequential compare register Comparator
Sample and hold circuit
Data register Decoder
ADCR0/1
A/D control register 0 A/D control register 1
ADCS0/1
16-bit reload timer 1 16-bit free-running timer zero detection
Operation clock
Prescaler
: Machine clock
58
F2MC-16LX bus
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
MB90460 Series
14. ROM Correction Function
In the case that the address of the instruction after the one that a program is currently processing matches the address configured in the detection address configuration register, the program forces the next instruction to be processed into an INT9 instruction, and branches to the interrupt process program. Since processing can be conducted using INT9 interrupts, programs can be repaired using batch processing. *Overview of the Rom correction Function * The address of the instruction after the one that a program is currently processing is always stored in an address latch via the internal data bus. Address match detection constantly compares the address stored in the address latch with the one configured in the detection address configuration register. If the two compared addresses match, the CPU forcibly changes this instruction into an INT9 instruction, and executes an interrupt processing program. * There are two detection address configuration registers : PADR0 and PADR1. Each register provides an interrupt enable bit. This allows you to individually configure each register to enable/prohibit the generation of interrupts when the address stored in the address latch matches the one configured in the detection address configuration register.
Block Diagram
Address latch
Internal data bus
PADR0 (24 bit) Detection address configuration register 0 PADR1 (24 bit) Detection address configuration register 1 PACSR ReReReReserved served served served AD1E
Reserved
Comparator
INT9 instruction (INT9 interrupt generation)
AD0E
Reserved
Address detection control register (PACSR)
Reseved : Make sure this is always set to "01" * Address latch Stores value of address output to internal data bus. * Address detection control register (PACSR) Set this register to enable/prohibit interrupt output when an address match is detected. * Detection address configuration register (PADR0, PADR1) Configure an address with which to compare the address latch value.
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MB90460 Series
15. ROM Mirroring Function Selection Module
The ROM mirroring function selection module can select what the FF bank allocated the ROM and see through the 00 bank according to register settings. Block Diagram
ROM mirroring register
F2MC-16LX bus
Address area FF bank 00 bank
ROM
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MB90460 Series
16. 512 Kbit Flash Memory
The 512 Kbit flash memory is allocated in the FEH to FFH banks on the CPU memory map. Like masked ROM, flash memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit. The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as "enable sector protect" cannot be used. Features of 512 Kbit flash memory * 64 kwords x 8 bits/32 kwords x 16 bits (16 k + 8 k + 8 k + 32 k) sector configuration * Automatic program algorithm (same as the Embedded Algorithm* : MBM29F400TA) * Installation of the deletion temporary stop/delete restart function * Write/delete completion detected by the data polling or toggle bit * Write/delete completion detected by the CPU interrupt * Compatibility with the JEDEC standard-type command * Each sector deletion can be executed (Sectors can be freely combined) . * Flash security feature * Number of write/delete operations 10,000 times guaranteed. * Flash reading cycle time (Min) 2 machine cycles * : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc. (1) Register configuration Flash Memory Control status register
7 6 RDYINT R/W 0 5 WE R/W 0 4 RDY R 1 3
Reserved
2 LPM1 W 0
1
Reserved
0 LMP0 R/W 0
Address : 0000AEH Read/write Initial value
INTE R/W 0
Bit number FMCS
W 0
W 0
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MB90460 Series
(2) Sector configuration of 512Kbit flash memory The 512 Kbit flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When accessed from the CPU, SA0 to SA3 are allocated in the FF bank registers, respectively.
Flash memory CPU address FFFFFFH SA3 (16 Kbytes) FFC000H FFBFFFH SA2 (8 Kbytes) FFA000H FF9FFFH SA1 (8 Kbytes) FF8000H FF7FFFH SA0 (32 Kbytes) FF0000H 70000H 78000H 77FFFH 7A000H 79FFFH 7C000H 7BFFFH *Writer address 7FFFFH
* : Programmer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel programmer. Programmer addresses are used to program/erase data using a general-purpose programmer.
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MB90460 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 -40 -55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 4 100 50 - 15 -4 - 100 - 50 300 +85 +150 (VSS = AVSS = 0.0 V) Unit V V V V V mA mA mA mA mA mA mA mA mA mA mW C C Average output current = operating current x operating efficiency Average output current = operating current x operating efficiency *3 Average output current = operating current x operating efficiency VCC AVCC* 1 AVCC AVR, AVR AVSS *2 *2 *4 *4 *3 Average output current = operating current x operating efficiency Remarks
Parameter
Symbol VCC
Power supply voltage Input voltage Output voltage Maximum clamp current "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
AVCC AVR VI VO ICLAMP
Total maximum clamp current | ICLAMP | IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
*1 : AVCC shall never exceed VCC when power on. *2 : VI and VO shall never exceed VCC + 0.3 V. *3 : The maximum output current is a peak value for a corresponding pin. *4 : * Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P46, P60 to P63 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. (Continued)
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MB90460 Series
(Continued)
* Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits: * Input/Output Equivalent circuits
Limiting resistance Protective diode
VCC P-ch
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB90460 Series
2. Recommended Operating Conditions
Symbol VCC VCC Smoothing capacitor Operating temperature Value Min 3.0 4.5 3.0 Max 5.5 5.5 5.5
(VSS = AVSS = 0.0 V) Unit V V V F Remarks Normal operation (MB90462, MB90467, MB90V460) Normal operation (MB90F462) Retains status at the time of operation stop Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS.
Parameter
Power supply voltage
CS
0.1
1.0
TA
-40
+85
C
* C pin connection circuit
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB90460 Series
3. DC Characteristics
Symbol VOH
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Pin name Condition VCC = 4.5 V, IOH = - 4.0 mA Value Min VCC - 0.5 0.7 VCC Typ Max 0.4 Unit V Remarks
Parameter "H" level output voltage
All output pins
"L" level output voltage
VOL
All pins except VCC = 4.5 V, P00 to P05 and IOL = 4.0 mA P30 to P35 P00 to P05, P30 to P35 VCC = 4.5 V, IOL = 12.0 mA
V
0.4 VCC + 0.3
V CMOS input pin
VIH
P00 to P07 P30 to P37 P50 to P57 P10 to P17 P20 to P27 P40 to P46 P60 to P63, RST MD pins P00 to P07 P30 to P37 P50 to P57 P10 to P17 P20 to P27 P40 to P46 P60 to P63, RST MD pins All input pins VCC = 5.5 V, VSS < VI < VCC VCC = 5.0 V, Internal operation at 16 MHz, Normal operation
V
"H" level input voltage
VIHS
0.8 VCC VCC = 3.0 V to 5.5 V (MB90462) VCC = 4.5 V to 5.5 V (MB90F462)
VCC + 0.3
V
CMOS hysteresis input pin
VIHM VIL
VCC - 0.3 VSS - 0.3

VCC + 0.3 0.3 VCC
V V
MD pin input CMOS input pin
"L" level input voltage
VILS
VSS - 0.3
0.2 VCC
V
CMOS hysteresis input pin
VILM Input leakage current IIL
VSS - 0.3 -5

VSS + 0.3 5
V A
MD pin input
40
50
mA
ICC Power supply current* VCC
VCC = 5.0 V, Internal operation at 16 MHz, When data written in flash mode programming of erasing VCC = 5.0 V, Internal operation at 16 MHz, In sleep mode
45
60
mA
ICCS
15
20
mA
(Continued)
66
MB90460 Series
(Continued)
Symbol (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Pin name Condition VCC = 5.0 V, Internal operation at 16 MHz, In Timer mode, TA = 25 C In stop mode, TA = 25 C Except AVCC, AVSS, C, VCC and VSS P00 to P07 P10 to P17 RST Value Min Typ Max Unit Remarks
Parameter
Power supply current*
ICTS VCC ICCH
2.5
5.0
mA

5
20
A pF
Input capacitance Pull-up resistance Pull-down resistance
CIN
10
80
RUP

25
50
100
k
RDOWN MD2
25
50
100
k
* : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock.
67
MB90460 Series
4. AC Characteristics
(1) Clock Timings Pin name X0, X1 X0, X1 X0 X0 (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol fC tHCYL f PWH PWL tCR tCF fCP tCP Value Min 3 3 62.5 10 1.5 62.5 Typ Max 16 32 333 5 5 16 666 Unit MHz ns % ns ns Recommened duty ratio of 30% to 70% External clock operation Remarks Crystal oscillator External clock *2
Parameter Clock frequency Clock cycle time Frequency fluctuation rate locked*1 Input clock pulse width Input clock rise/fall time Internal operating clock Internal operating clock cycle time
MHz Main clock operation ns Main clock operation
*1 : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. *2 : Internal operating clock frequency must not be over 16 MHz.
f =
fo
x 100 (%)
Center frequency
+ fo -
tHCYL 0.8 VCC
X0
0.2 VCC PWH tCF PWL tCR
68
MB90460 Series
Relationship between internal operating clock frequency and power supply voltage
Operation guarantee range of MB90F462 5.5 Power supply voltage VCC (V)
4.5
3.3 3.0 Operation guarantee range of MB90462, MB90467, MB90V460
Operation guarantee range of PLL
1
3
8 Internal clock fCP (MHz)
12
16
Relationship between oscillating frequency and internal operating clock frequency
Multiplied- Multiplied- Multipliedby-4 by-3 by-2 Multipliedby-1
16 Internal clock fCP (MHz)
12 9 8 Not multiplied
4
3
4
8 Oscillation clock fC (MHz)
16
The AC ratings are measured for the following measurement reference voltages * Input signal waveform Hysteresis Input Pin
0.8 VCC 0.2 VCC
* Output signal waveform Output Pin
2.4 V 0.8 V
Pin other than hystheresis input/MD input
0.7 VCC 0.3 VCC
69
MB90460 Series
(2) Reset Input Timing
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Pin Condition Value Min 4 tCP Oscillation time of oscillator + 4 tCP* Max Units ns ms Remarks Under normal operation In stop mode
Parameter
Symbol
Reset input time
tRSTL
RST
* : Oscillation time of oscillator is time that amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between handreds s to several ms. In the external clock, the oscillation time is 0 ms. * In stop mode
tRSTL
RST
0.2 VCC 90% of amplitude 0.2 VCC
X0
Internal operation clock
4 tCP Oscillation time of oscillator Oscillation setting time Instruction execution
Internal reset
70
MB90460 Series
(3) Power-on Reset
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name tR tOFF VCC VCC Condition Value Min 0.05 4 Max 30 Unit ms ms Due to repeated operations Remarks
Parameter Power supply rising time Power supply cut-off time
Note : VCC must be kept lower than 0.2 V before power-on. The above values are used for causing a power-on reset. Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the power supply using the above values.
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock.
VCC 3.0 V VSS
RAM data Hold
It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
71
MB90460 Series
(4) UART0 to UART1
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK0 to SCK1 SCK0 to SCK1 SOT0 to SOT1 CL = 80 pF + 1 TTL for an output pin of SCK0 to SCK1 internal shift clock SIN0 to SIN1 mode SCK0 to SCK1, SIN0 to SIN1 SCK0 to SCK1 SCK0 to SCK1 SCK0 to SCK1, CL = 80 pF + 1 TTL SOT0 to SOT1 for an output pin of external shift clock SCK0 to SCK1, mode SIN0 to SIN1 SCK0 to SCK1, SIN0 to SIN1 Condition Value Min 8 tCP -80 100 60 4 tCP 4 tCP 60 60 Max 80 150 Unit Remarks ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Note : * These are AC ratings in the CLK synchronous mode. * CL is the load capacitance value connected to pins while testing. * tCP is machine cycle time (unit : ns) .
72
MB90460 Series
* Internal shift clock mode
SCK
0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
SCK
0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC
0.8 VCC
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
73
MB90460 Series
(5) Resources Input Timing
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Pin name IN0 to IN3, SNI0 to SNI2 TIN0 to TIN1 PWI0 to PWI1 DTTI0, DTTI1 Condition Value Min Max Unit Remarks
Parameter
Symbol
Input pulse width
tTIWH tTIWL
4 tCP
ns
0.8 VCC*1
0.8 VCC 0.2 VCC*2 tTIWH tTIWL 0.2 VCC*2
*1 : 0.7 VCC for PWI0 input pin *2 : 0.3 VCC for PWI0 Input pin
(6) Trigger Input Timimg
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tTRGH tTRGL Pin name INT0 to INT7 Condition Value Min 5 tCP Max Unit ns Remarks
Parameter Input pulse width
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
74
MB90460 Series
5. A/D Converter Electrical Characteristics
Symbol Pin name
(3.0 V AVR - AVSS, VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Min AVSS - 1.5 LSB AVSS - 3.5 LSB AVR - 3.5 LSB AVR - 6.5 LSB Typ 10 AVSS + 0.5 LSB AVSS + 0.5 LSB AVR - 1.5 LSB AVR - 1.5 LSB Max 3.0 5.0 2.5 1.9 AVSS + 2.5 LSB AVSS + 4.5 LSB AVR + 0.5 LSB AVR + 1.5 LSB Unit bit LSB For MB90F462, MB90462, MB90467 LSB For MB90V460 LSB LSB Remarks
Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage
VOT
AN0 to AN7
mV For MB90F462, MB90462, MB90467 mV For MB90V460 mV For MB90F462, MB90462, MB90467 mV For MB90V460 Actual value is specified as a sum of values specified in ADCR0 : CT1, CT0 and ADCR0 : ST1, ST0. Be sure that the setting value is greater than the min value Actual value is specified in ADCR0 : ST1, ST0 bits. Be sure that the setting value is greater than the min value
Full-scale transition voltage
VFST
AN0 to AN7
Conversion time
6.125
1000
s
Sampling period
AN0 to AN7 AN0 to AN7 AVR
2
s
Analog port input current Analog input voltage Reference voltage Power supply current
IAIN VAIN IA IAH*
AVSS AVSS + 2.7
2.3 2 140 0.9
10 AVR AVCC 6 5 5 260 1.3 5 4
A V V mA For MB90F462, MB90462, MB90467 mA For MB90V460 A A A LSB * For MB90F462, MB90462, MB90467 *
AVCC
Reference voltage supply current Offset between channels
IR IRH*
AVR AN0 to AN7

mA For MB90V460
* : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 5.0 V) 75
MB90460 Series
6. A/D Converter Glossary
Resolution : Linearity error : Analog changes that are identifiable with the A/D converter The deviation of the straight line connecting the zero transition point ("00 0000 0000" "000000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF 3FE 3FD {1 LSB x (N - 1) + 0.5 LSB} Actual conversion value 1.5 LSB
Digital output
004 003 002 001 AVss Analog input
VNT (Measured value) Actual conversion value Theoretical characteristics 0.5 LSB AVR
Total error for digital output N = 1 LSB = (Theoretical value)
VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB [V]
[LSB]
AVR - AVSS 1024
VOT (Theoretical value) = AVSS + 0.5 LSB [V] VFST (Theoretical value) = AVR - 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
76
MB90460 Series
(Continued)
Linearity error
3FF 3FE 3FD Digital output Actual conversion value {1 LSB x (N - 1) + VOT }
Differential linearity error
Theoretical characteristics N+1 VFST (Measured value) Actual conversion value Digital output N
004 003 002 001 AVss Analog input
VNT (measured value) Actual conversion value Theoretical characteristics VOT (Measured value) AVR
N-1
V (N + 1) T (Measured value) VNT (Measured value) Actual conversion value AVR Analog input
N-2
AVss
Linearity error of = digital output N Differential linearity error = of digital output N 1 LSB =
VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N + 1) T - VNT -1 [LSB] 1 LSB VFST - VOT 1022 [V]
[LSB]
VOT : Voltage at transition of digital output from "000H" to "001H" VFST : Voltage at transition of digital output from "3FEH" to "3FFH"
77
MB90460 Series
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit recommends about 5 k or lower (sampling period = 2.0 s @machine clock of 16 MHz) . When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient.
* Analog input circuit model
R Comparator
Analog input
C
MB90462, MB90F462, MB90467 R 2.6 K, C 28 pF MB90V460 R 3.2 K, C 30 pF Note : Listed values must be considered as standards. * Error The smaller the absolute value of | AVR - AVSS |, the greater the error would become relatively.
8. Flash Memory Program and Erase Performances
Parameter Sector erase time Chip erase time Word (16 bit width) programming time Erase/Program cycle TA = + 25 C VCC = 3.0 V Condition Value Min 10,000 Typ 1 5 16 Max 15 3,600 Unit s s s cycle Remarks Excludes 00H programming prior erasure Excludes 00 H programming prior erasure Excludes system-level overhead
78
MB90460 Series
s EXAMPLE CHARACTERISTICS
* Power Suppy Current of MB90462, MB90467 ICCH vs. VCC TA = 25 C, external clock input
40 35 30 25
ICCH (mA) FC = 12 [MHz] FC = 10 [MHz] FC = 8 [MHz] FC = 16 [MHz]
ICCS vs. VCC TA = 25 C, external clock input
20 18 16 14 ICCS (mA) 12 10 8 6 FC = 4 [MHz] FC = 2 [MHz] FC = 12 [MHz] FC = 10 [MHz] FC = 8 [MHz] FC = 16 [MHz]
20 15 10 5 0 2 3 4
VCC (V)
FC = 4 [MHz] FC = 2 [MHz]
4 2 0 2 3 4 VCC (V) 5
6
5
6
VCC - VOH vs. IOH TA = 25 C, VCC = 4.5 V
1000 900 800 700 VCC -VOH (mV) 600 VOL (V) 500 400 300 200 100 0 0 1000 900 800 700 600 500 400 300 200 100
VOL vs. IOL TA = 25 C, VCC = 4.5 V
-2
-4
-6
-8
- 10
- 12
0 0 2 4 6 IOL (mA) 8 10 12
IOH (mA)
79
MB90460 Series
* Power Suppy Current of MB90F462 ICCH vs. VCC TA = 25 C, external clock input
40 35 30 25
ICCH (mA) FC = 12 [MHz] FC = 16 [MHz]
20 18 16 14 FC = 16 [MHz] FC = 12 [MHz] FC = 10 [MHz] FC = 8 [MHz] FC = 4 [MHz] FC = 2 [MHz]
ICCS vs. VCC TA = 25 C, external clock input
20 15
ICCS (mA)
FC = 10 [MHz] FC = 8 [MHz]
12 10 8 6
10 5 0 2 3 4
VCC (V)
FC = 4 [MHz] FC = 2 [MHz]
4 2 0 2 3 4 VCC (V)
5
6
5
6
VCC - VOH vs. IOH TA = 25 C, VCC = 4.5 V
1000 900 800 700 VCC - VOH (mV) 600 VOL (V) 500 400 300 200 100 0 0 2 4 6 IOH (mA) 8 10 12 1000 900 800 700 600 500 400 300 200 100 0 0
VOL vs. IOL TA = 25 C, VCC = 4.5 V
2
4
6 IOL (mA)
8
10
12
80
MB90460 Series
s ORDERING INFORMATION
Part number MB90F462PFM MB90462PFM MB90467PFM MB90F462PF MB90462PF MB90467PF MB90F462P-SH MB90462P-SH MB90467P-SH Package 64-pin Plastic LQFP (FPT-64P-M09) 64-pin Plastic QFP (FPT-64P-M06) 64-pin Plastic SH-DIP (DIP-64P-M01) Remarks
81
MB90460 Series
s PACKAGE DIMENSIONS
64-pin Plastic QFP (FPT-64P-M06)
24.700.40(.972.016) 20.000.20(.787.008)
51 33
Note : Pins width and pins thickness include plating thickness.
0.170.06 (.007.002)
52
32
18.700.40 (.736.016) 14.000.20 (.551.008) INDEX Details of "A" part 3.00 -0.20 .118 -.008
20
+0.35 +.014
(Mounting height)
64
0~8
1 19
1.00(.039)
0.420.08 (.017.003)
0.20(.008)
M
0.25 -0.20 1.200.20 (.047.008)
+0.15 +.006
.010 -.008 (Stand off)
"A" 0.10(.004)
C
2001 FUJITSU LIMITED F64013S-c-4-4
Dimensions in mm (inches)
82
MB90460 Series
64-pin Plastic LQFP (FPT-64P-M09)
Note : Pins width and pins thickness include plating thickness.
14.000.20(.551.008)SQ 12.000.10(.472.004)SQ
48 33
0.1450.055 (.0057.0022)
49
32
0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8
64 17
1
16
"A"
0.65(.026)
0.320.05 (.013.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.13(.005)
M
C
2001 FUJITSU LIMITED F64018S-c-2-4
Dimensions in mm (inches)
83
MB90460 Series
64-pin Plastic SH-DIP (DIP-64P-M01)
58.00 -0.55 2.283 -.022
+0.22 +.009
Note : Pins width and pins thickness include plating thickness.
INDEX-1 17.000.25 (.669.010) INDEX-2
4.95 -0.20 .195 -.008
+0.70 +.028
0.70 -0.19 .028 -.007
+0.50 +.020
3.30 -0.30 .130
+0.20 +.008 -.012 +0.40 -0.20 +.016 -.008
0.270.10 (.011.004) 1.378 .0543 1.778(.0700) 0.470.10 (.019.004) 0.25(.010)
M
19.05(.750) 0~15
1.00 -0
+0.50 +.020
.039 -.0
C
2001 FUJITSU LIMITED D64001S-c-4-5
Dimensions in mm (inches)
84
MB90460 Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0112 (c) FUJITSU LIMITED Printed in Japan

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